Reasons for the occurrence of variation in semiconductor devices include, for example, fabrication variation, operating environment variation, tool error, and so forth. Among these, fabrication variations include for example, shift of mask optical proximity correction (OPC), lithography misalignment, unevenness in etching and chemical mechanical polishing (CMP). Furthermore, operating environment variations include, for example, variation in power supply voltage, and temperature variation. Tool errors include, for example, error measurement by electronic design automation (EDA) tools.
Recently, with advances in semiconductor fine processing technology, effects of fabrication variation on circuit characteristics due to shrinkage in transistor dimension are becoming evident, and as a result, various types of proposals are being made with regard to layouts for reducing variations in semiconductor devices. Among these, a current source cell layout structure in which error in the current value of a current source, due to a variation in a fabrication process, is reduced by devising an arrangement layout of current source cells, and in which linearity is improved, is disclosed in, for example, Patent Document 1.
Patent Document 1 discloses a current source cell layout structure forming a constant current source having a required current amount by combining, for a current source cell matrix in which current source cells are arranged in a matrix, a plurality of the respective current source cells. In order to solve the problem that, due to a variation that has a fixed tendency such as a process variation or the like, current values of respective current sources differ largely at two ends of the current source cell matrix, and linearity is not obtained, the configuration is such that a current course cell matrix is divided into a plurality of blocks arranged symmetrically with respect to the center of the matrix arrangement, and constant current sources are formed from combinations of equal numbers of current source cells selected from each block in a row or a column direction. In Patent Document 1, the current source cells with the matrix arrangement as center are non-active (unused) as shown in FIG. 5 of Patent Document 1, or are removed as shown in FIGS. 7A and 7B of Patent Document 1. It is to be noted that this Patent Document 1 does not disclose a measure for variation in a current mirror configuration provided with a reference element.
Patent Document 2 discloses a current source cell layout structure in which current source cells are arranged in a matrix, wherein the configuration is such that, even if output current of a current source cell has a variation in a peak form or a valley form, the variation is eliminated by combining current source cells so as to reduce the variation, and variation due to IR drop due to wiring resistance is mostly eliminated.
Patent Document 3 discloses a semiconductor integrated circuit with, as a function cell structure having an arrangement of elements forming a current mode logic (CML) circuit, a cross type structure in which the elements are arranged so as to have rotational symmetry every 90° with respect to cell center point, or a cross type structure arranged by folding axis-symmetrically with respect to X and Y axes passing through the cell center.
Below, a description is given concerning a current mirror which includes a second current source that outputs a second current (mirror current) corresponding to a first current that flows in a first current source. FIG. 1 shows a circuit configuration of a well known current mirror. Referring to FIG. 1, MOS transistors M1 and M2, have sources connected to a power supply VSS, and gates coupled together. The MOS transistor M1 has a drain connected to a gate. Since a drain-to-source voltage (VGS1) of the MOS transistor M1 is higher than a threshold voltage VTH, and a drain-to-gate voltage (VDG1) is 0V, the MOS transistor M1 operates in a saturated region. When a drain-to-source voltage (VDS2) of the MOS transistor M2 is larger than VGS1-VTH1, both of the MOS transistors M1 and M2 operate in a saturated region. A drain-to-source current IDS of a MOS transistor in a saturated region is given by the following.
                              I          DS                =                              β            2                    ⁢                                    (                                                V                  GS                                -                                  V                  TH                                            )                        2                    ×                      (                          1              +                              λ                ⁢                                                                  ⁢                                  V                  DS                                                      )                                              (                  1          ⁢                      -                    ⁢          1                )            
In (1-1),
VGS is a gate-to-source voltage, VTH is a threshold voltage,
VDS is a drain-to-source voltage,
λ is a channel length modulation coefficient, and
β is a gain coefficient.
β is given by the following Equation (1-2), where μ is a channel mobility, Cox is a gate capacitance per unit area, W is a channel width, and L is a channel length.
                    β        =                  μ          ⁢                                          ⁢                                    C              OX                        ⁡                          (                              W                L                            )                                                          (                  1          ⁢                      -                    ⁢          2                )            
With drain-to-source currents ID of the MOS transistors M1 and M2, given by Equation (1-1), as IIN and IOUT, respectively, a matching accuracy is given by IOUT/IIN.
                                          I            OUT                                I            IN                          =                                            (                                                W                  2                                /                                  L                  2                                            )                        ⁢                                          (                                                      V                                          GS                      ⁢                                                                                          ⁢                      2                                                        -                                      V                                          TH                      ⁢                                                                                          ⁢                      2                                                                      )                            2                        ⁢                          (                              1                +                                                      λ                    2                                    ⁢                                      V                                          DS                      ⁢                                                                                          ⁢                      2                                                                                  )                                                          (                                                W                  1                                /                                  L                  1                                            )                        ⁢                                          (                                                      V                                          GS                      ⁢                                                                                          ⁢                      1                                                        -                                      V                                          TH                      ⁢                                                                                          ⁢                      1                                                                      )                            2                        ⁢                          (                              1                +                                                      λ                    1                                    ⁢                                      V                                          DS                      ⁢                                                                                          ⁢                      1                                                                                  )                                                          (        2        )            
If, with regard to the MOS transistors M1 and M2, the gate-to-source voltages VGS1 and VGS2, the threshold voltages VTH1 and VTH2, the drain-to-source voltages VDS1 and VDS2, and the channel length modulation coefficients λ1 and λ2 are assume to be equal, or if a channel length modulation effect is assumed to be negligible, a ratio of input current IIN and output current IOUT (current gain) is given by the following Equation (3).
                                          I            OUT                                I            IN                          =                              (                                          W                2                            /                              L                2                                      )                                (                                          W                1                            /                              L                1                                      )                                              (        3        )            
When W/L of the MOS transistors M1 and M2 are the same as each other, IINN=IOUT. In order to a current ratio of the input current IIN and the output current IOUT to be 1:N, for example, the MOS transistor M1 is connected to N MOS transistors M2 having the same W, which are connected in parallel.
Consideration is given to variation in characteristic of MOS transistors forming a current mirror, for example, by separating components of variation corresponding to a Gaussian noise (in Non-Patent Document 1, referred to as a local variation), and variation due to a position (in Non-Patent Document 1, referred to as a global variation). An overview is given below of transistor variation, based on a description of Non-Patent Document 1. It is to be noted that in what follows, the description is given referring to a variation model described in Non-Patent Document 1, for convenience of the description. However, this does not exclude any variation model other than the variation model described in Non-Patent Document 1.
Regarding a transistor circuit characteristic P, with a characteristic PO of a transistor M0 at a point of origin (0, 0) as a reference, a characteristic Pi of a transistor Mi at (Δx, Δy) is given by Equation (4), as a first order model. That is, the variation of the characteristic Pi (a bar in Equation (4) indicates an average) is determined by a position (Δx, Δy) with respect to the characteristic PO of the transistor M0 (Non-Patent Document 1, page 26, Equation (2.8)).
                                          P            _                    i                =                                            P              _                        0                    +                                                    ∂                P                                            ∂                x                                      ⁢            Δ            ⁢                                                  ⁢            x                    +                                                    ∂                P                                            ∂                y                                      ⁢            Δ            ⁢                                                  ⁢            y                                              (        4        )            
An output current error of a current mirror including a MOS transistor (M1 in FIG. 1) receiving an input current IIN as input and a MOS transistor (M2 in FIG. 1) outputting an output current IOUT, is represented by a dimension WL of the MOS transistors and a distance (Δx) between transistors, as in the following Equation (5) (Non-Patent Document 1, page 40, Equation (2.46)).
                                          Δ            ⁢                                                  ⁢            I                                I            IN                          =                                                            I                OUT                            -                              I                IN                                                    I              IN                                ≅                                                                      A                                      Δ                    ⁢                                                                                  ⁢                    I                                                                    WL                                            ·                              (                rand                )                                      +                                                                                ∂                    I                                                        ∂                    x                                                  ·                Δ                            ⁢                                                          ⁢              x                                                          (        5        )            
In Equation (5), “rand” in the first term on the right hand side is a standard normal distribution, and AΔI is a variation model parameter. The first term in Equation (5) corresponds to local variation of Gaussian noise, and the second term corresponds to variation depending on distance (global variation). When transistor size (gate size) WL is large, the local variation is small. Conversely, the smaller the gate size of a transistor, the larger the local variation is.
From the second term of Equation (5), the variation component that depends on a distance of the output current error of the current mirror is proportional to the distance (Δx) between centers of the MOS transistors (M1 and M2 in FIG. 1) that form the current mirror. That is, the farther apart the distance between the transistors, the more the output current errors differ. With regard to a characteristic q other than a transistor output current error ((IOUT−IIN)/IIN), similar to Equation (5), a relative accuracy thereof Δq (index indicating matching level of transistor characteristic) is represented by a transistor gate size WL and a distance Δx between transistors, as in the following Equation (6) (Non-Patent Document 1, page 41, Equation (2.54)).
                              Δ          ⁢                                          ⁢          q                =                                                            A                                  Δ                  ⁢                                                                          ⁢                  q                                                            WL                                      ·                          (              rand              )                                +                                                                      ∂                  q                                                  ∂                  x                                            ·              Δ                        ⁢                                                  ⁢            x                                              (        4        )            
The local variation of the first term of Equation (6) indicates that a fluctuation range of the transistor characteristic is determined by the gate size (WL) of the transistor.
With regard to current mirror transistor layout, a configuration in which two transistors B-1 and B-2 on an output side are laid out in parallel in line is shown in FIGS. 2A and 2B. FIG. 2A is a circuit diagram, and FIG. 2B is a layout diagram. As shown in FIG. 2A, sources of MOS transistors A, B-1, and B-2 are connected to a power supply VSS, gates are connected in common, and a drain and gate of the MOS transistor A are connected.
In FIG. 2B, rectangular regions of A, B-1, and B-2 indicate gates (electrodes) of the transistors A, B-1, and B-2, with a short side corresponding to a gate length (channel length) L and a long side which corresponds to a width of a diffusion layer, corresponding to a gate width (channel width) W. A rectangular region on both sides of the gate represents a metal interconnect (1 layer) on a diffusion layer (drain, source), and squares indicate contact (contact hole, plug). The transistors B-1 and B-2 are formed from a unit cell structure identical to the transistor A. Circuit parameters of the transistors A, B-1 and B-2, such as channel width (W) and channel length (L), being gate size, are identical to one another. A sum of output currents (drain currents) of the transistors B-1 and B-2 is double an input current of the transistor A.
In FIG. 2B, if a distance in a channel direction between the transistor A and the transistor B-1 (distance between gate centers) is Δx, a distance between the transistor A and the transistor B-2 is 2 Δx. From Equation (5), a difference in distance dependent variations of output current errors of the transistor A and the transistor B-2 is approximately double a difference in distance dependent variations of an output current errors of the transistor A and the transistor B-1.
It is to be noted that, with respect to the current mirror, there are various proposals besides a configuration in which the transistors B-1 and B-2 are laid out in parallel, as in FIG. 2B (Non-Patent Document 1 and Non-Patent Documents 2 and 3). For example, the current mirror can be into a point symmetry type layout such as a layout (common centroid) in which transistors forming a pair are divided into two arranged at opposing corner positions, a line symmetry type layout in which transistors are arranged in parallel or transistors are folded and arranged in parallel, or the like. Among these, the point symmetry type transistor pair is not affected by global variation.    [Patent Document 1] US2001/054975A1, U.S. Pat. No. 6,433,721B2 corresponding to JP Patent Kokai Publication No. JP-P2002-009247A    [Patent Document 2] US2007/126617A1, U.S. Pat. No. 7,420,495B2 corresponding to JP Patent Kokai Publication No. JP-P2007-158166A    [Patent Document 3] U.S. Pat. No. 6,075,260A corresponding to JP Patent No. 3169883    [Non-Patent Document 1] “Research concerning Performance Variation Analysis of Integrated Circuits”, Okada, Kenichi, Internet URL: http://repository.kulib.kyoto-u.ac.jp/dspace/bit stream/2433/59292/1/D_Okada_Kenichi.pdf    [Non-Patent Document 2] H. Elzinga, “On the Impact of Spatial Parametric Variations on MOS Transistor Mismatch”, Proceedings of IEEE International Conference of Microelectronic Test Structures, Vol. 9, pp. 173-177, March 1996.    [Non-Patent Document 3] J. Bastos, M. Steyert, B. Graindourze, and W. Sansen, “Matching of MOS Transistors with Different Layout Styles”, Proceedings of IEEE International Conference of Microelectronic Test Structures, Vol. 9, pp. 17-18, March 1996.